The present invention relates to an image sensor, in particular of the contact-type, and a plurality of image sensor chips so mounted and connected as to constitute such an image sensor. The image sensor of this type may for example be used as a reading part of an image scanner reading image information.
FIG. 1 is a circuit diagram for an image sensor chip (integrated circuit) in the prior art, such as is disclosed, for example, on page 20 of a catalog of Mitsubishi Denki Kabushiki Kaisha (title: "Mitsubishi Contact-type Image Sensors" No. H-C0274-B HQ 9007 (ROD), published in July, 1990).
Referring to the figure, a plurality of photocells 1-1 to 1-N, which may be formed of photo-transistors, receive light from a document or the like (the depiction of which is omitted) and convert the brightness of received light into electrical signals, which are called image signals, in time with clock pulses CLK, shown in FIG. 2. The photocells are arranged in a straight line. An electrode pad 2 is provided for input of the electric power V.sub.DD that is supplied to the photocells 1.
A signal line 3 is provided for transmission of the image signals from the photocells 1-1 to 1-N. Channel select switches 4-1 to 4-N which are composed, for example, of n-channel MOS transistors, are provided for the respective photocells 1-1 to 1-N, and selectively connect the corresponding photocell to the signal line 3.
An electrode pad 6 is provided for input of a shift signal (also called a start pulse) SI having a duration of one clock cycle and having a rising edge coincident with the falling edge of a clock pulse as shown in FIG. 2. The shift signal that has been entered is shifted sequentially through a shift register 5. Another electrode pad 7 is for input of the clock pulses CLK for the shift register 5.
The shift register 5 serves as a switch driver circuit, being activated by the shift signal SI, and performing successive closure of the channel select switches 4-1 to 4-N in accordance with the clock pulses CLK. This may be paraphrased by "passage of the shift signal SI through the shift register 5." Specifically, the shift register 5 comprises cascaded D-type flip-flops 5-1 to 5-N provided for the respective channel select switches 4-1 to 4-N: Q outputs of the flip-flops (except the last flip-flop 5-N) are connected to the D input terminals of the next flip-flops, the Q output of the last flip-flop 5-N forms the output of the shift register 5. The Q outputs of the flip-flops 5-1 to 5-N are connected to the control terminals of the channel select switches, i.e., the gates of the n-channel MOS transistors 4-1 to 4-N. The Q output of the first flip-flop 5-1 rises at the falling edge of a clock pulse CLK and one clock cycle after the rise of the shift pulse SI, and the Q outputs of the flip-flops 5-1 to 5-N are successively made High for a duration of one clock cycle, with the rising edge of each Q output being coincident with the falling edge of the clock pulse. As a result, the channel select switches 4-1 to 4-N are successively made ON or conductive, so that the image signals from the photocells 1-1 to 1-N are output successively (in the illustrated example, in the order of 1-1, 1-2, 1-3, . . . 1-N) via the common signal line 3 and through an image signal output (SIG) terminal 11.
A flip-flop 8 is configured to shape the shift signal that has been shifted through the shift register 5 so as to form a shaped signal SO which is output via an electrode pad 9 and supplied to the next image sensor chip as an input shift signal SI therefor. More specifically, the Q output of the flip-flop 8 rises at the rising edge of a clock pulse, and 1/2 clock cycle after the rise of the Q output of the last flip-flop 5-N in the shift register 5. By providing such a pulse to the next image sensor chip, the Q output of the first flip-flop 5-1 in the shift register in the next image sensor chip rises one clock cycle after the rise of the Q output of the last flip-flop 5-N in the shift register 5 in the image sensor chip under consideration.
Another flip-flop 10 is set by the shift signal SI input to the electrode pad 6 and reset by the output SO of the flip-flop 8. In other words, the flip-flop 10 continues to output a High-level signal, after the image sensor chip is activated by the input shift signal SI and until the end of the operation of the shift register 5, i.e., after the input of the shift signal SI to the flip-flop 5-1 until the output of the shift signal SO from the flip-flop 8.
An electrode pad 11 is for sending the image signals on the signal line 3 to the outside of the sensor.
A chip select switch 12 connects the signal line 3 to the electrode pad 11 in accordance with the output of the flip-flop 10 throughout the period in which the photocells 1-1 to 1-N within the chip are driven. The chip select switch 12 is closed or conductive when it receives a High level signal from the flip-flop 10.
A reset switch 13 connects, at regular intervals in accordance with the clock pulses, the signal line 3 to an electrode pad 14, which is grounded.
Both the reset switch 13 and the chip select switch 12 above described may be formed, for example, of n-channel MOS transistors.
FIG. 3 is a block diagram showing a contact-type image sensor formed from a plurality of sensor chips, 15-1, 15-2 and 15-3, each of which is configured as shown in FIG. 1. The image sensor chips 15-1, 15-2 and 15-3 are all mounted on a common board, schematically illustrated by a block of dotted line 30, and arranged in a straight line, and cascaded by means of the respective electrode pads 6 and 9 so that the initial shift signal SIO is applied from a terminal 26 to the electrode pad 6 of the first image sensor chip 15, and the output shift signal SO from the electrode pad 9 of each image sensor chip 9 is applied as the input shift signal SI to the electrode pad 6 of the succeeding image sensor chip 15.
Although the image sensor is shown to be formed of three sensor chips, it may be formed of any other number of sensor chips.
The electrode pads 7 are connected together to a terminal 27 on the board 30. Clock pulses CLK are applied from outside to the terminal 27 and then to the electrode pads 7 of the sensor chips 15.
The electrode pads 11 are connected together to a terminal 31 on the board. The image signals from the photocells in the sensor chips are output through the respective electrode pads 11 and all to the terminal 31.
FIG. 4 is a timing diagram showing the operation of the image sensor chip 15, in which SI designates the shift signal, CLK designates the clock pulse, and SIG designates the image signal.
The first image sensor chip 15 receives the initial shift signal SI (the initial shift signal is also denoted by SIO) supplied from the terminal 26 and the clock pulse CLK supplied from the terminal 27 at the electrode pads 6 and 7 respectively. This shift signal SI is read into the shift register 5 at the falling edge of a clock pulse CLK, and is passed sequentially through the flip-flops within the shift register 5 in synchronism with the clock pulse CLK. Accordingly a driver signal is applied sequentially from the shift register 5 to each of the channel select switches 4-1 to 4-N, which are thereby closed successively. While each channel select switch is closed, the image signal from the corresponding photocell is output via the signal line 3 and through the SIG terminal 11. When the channel select switch is opened, the output of the image signal from the corresponding photocell is stopped, and the the shift signal is transferred to the flip-flop in the next stage.
The shift signal that has been passed out of the shift register 5 is sent to the flip-flop 8, and becomes the shift signal for the next image sensor chip 5, and is output via the electrode pad 9.
Meanwhile, as the channel select switches 4 are closed sequentially one channel at a time, the image signal SIG generated at the photocell 1 corresponding to the closed channel select switch is sent sequentially to the common signal line 3.
The flip-flop 10 continues to output a High-level signal and hence the chip select switch 12 is ON (conductive) throughout the period in which the channel select switches are ON. Accordingly the image signal SIG, which has been sent from the photocells 1-1 to 1-N to the signal line 3 is output via the chip select switch 12 to the electrode pad 11, and then to the terminal 31.
When all of the photocells have been selected, the shift signal is supplied from the shift register 5 to the flip-flop 8. As the flip-flop 10 is reset by the Q output of the flip-flop 8, the chip select switch 12 is turned off.
A reset switch 13 is interposed between the grounded electrode pad 14 and the signal line 3, and is turned on during a High-level period of clock pulse CLK. Accordingly, the signal line 3 is discharged while the clock pulses CLK is High, and the photocell (the emitter of the photo-transistors forming the photocell) which has just finished outputting the image signal SIG (over the Low period of the clock signal CLK) is lowered to the ground potential. In other words, it is forcibly reset.
The voltage level (potential of the signal line 3) is thereby forcibly lowered to the ground potential immediately after the image signal is output from each photocell. If the signal line 3 were not forcibly lowered to the ground level after the image signal is read from each photocell, the remaining potential level would be added to the potential level of the image signal subsequently read out, so accuracy of the image signal would be degraded.
The subsequent image sensor chips 15 operate in the same manner, using the signal SO from the preceding image sensor chip 15 as the input shift signal SI, and receiving the clock pulse CLK from the terminal 27.
There may be further provided a capacitor 28 (normally of about several hundred pF). The function of the capacitor 28 in this circuit is to shape the waveform of the image signal (FIG. 4) from the SIG terminals 11 of the image sensor chips 15-1 to 15-3, into an integral wave, as shown in FIG. 5 at (c), before the signal is output through the SIG terminal 31.
FIG. 5 is a time chart showing the signals on the terminals of a contact-type image sensor. As is shown in the figure, the signal for one line, which is output on the terminal 31 from this contact-type image sensor, consists of an image signal portion that includes image information and a blanking portion that does not.
FIG. 6 is a timing diagram showing an enlargement of the portion A in FIG. 5, in which VB is a level of the signal during the blanking portion. Due to the fact that the signal line 3 is at a high impedance, the level VB is an indeterminate value that is affected, inter alia, by the parasitic capacitance CF shown by broken line in FIG. 3.
Since image sensor chips in accordance with the prior art are configured as described above, the level VB that is present in the blanking portion is indeterminate. Thus the reference level is not present in the output signal, making it necessary to establish an absolute value for the dark output. This level changes due to external factors such as temperature or voltage, with concomitant changes in image brightness leading to degradation of image quality.
Another problem associated with the prior art contact-type image sensor will next be described with reference to FIG. 7.
In the above-described prior-art image sensor chips, when the operation of the shift register 5 is completed, i.e., when the image signal from the photocells 1-1 to 1-N is all output through the SIG terminal 11, the chip select switch 12 is opened, so even if the switch 13 is closed, the potential on the electrode pad 11 and the line connecting the pads 11 of all the sensor chips to the external terminal 31 is not forcibly lowered to the ground level. As a result, as shown at (b) in FIG. 7, when the image signals of each image sensor chip for the image sensor are all output, the potential of the image signal on the terminal 31 is not lowered to the ground level (because of the remaining charge on the capacitor 28), and, a condition is brought about, in which, despite that the image signal is all output, the output of the image signal is still at a certain level. Accordingly, it is not possible to obtain accurate image signals.
In order to remove the remaining charge from the capacitor 28, a switch 29 may be additionally provided and controlled to be conductive when the clock pulse CLK is High. Then, an accurate image signal is obtained as shown at (c) in FIG. 7. The use of the external switch 29 however requires a space on the board 30 (on which the chips are also mounted) and increases the cost.